Half Adder
A half adder is a digital circuit that performs the addition of two single binary digits. It has two inputs, typically labeled A and B, and two outputs: the sum (S) and the carry (C). The half adder can only handle one bit at a time and does not account for any carry from previous additions.
8 Key excerpts on "Half Adder"
eBook - ePubSemiconductor Basics
A Qualitative, Non-mathematical Explanation of How Semiconductors Work and How They are Used
- George Domingo(Author)
- 2020(Publication Date)
- Wiley(Publisher)
...We call the module in Figure 11.18 a Half Adder because it adds only two single‐digit numbers. Basically, they operate on one number at a time. The Half Adder can be implemented using XOR and AND modules. If the inputs X and Y are 0, the outputs of both the XOR output, V S for signal value and the AND output, V C, for the carry‐on result are 0. The output of the XOR, the third column in the truth table, is 1 only if one of the inputs is 1; otherwise the output is 0. The output of the AND circuit, the fourth column of the truth table, is 1 only if both X and Y are 1. This agrees with the truth table for the sum of two binary numbers, which I show in the fifth column. The symbol for a Half Adder is just a square box with two inputs, X and Y, and two outputs, V S and V C, with the word “Half Adder” in the middle of the box for clarity. Figure 11.18 The Half Adder circuit (left), the truth table (right), and its symbol (lower middle). 11.9 The Full Adder The problem with the Half Adder is that it can add only two single‐digit numbers, similar to the decimal system limited to adding just two numbers between zero and nine. What happens when we want to add larger numbers like 15 + 3? In addition to the 5 and the 3, we have the digit 1 (which is not 1 but a 10) that we need to include in our sum. In the binary system we have a similar situation. With the Half Adder we can add 1 + 0 or 1 + 1 but how about 10 to 1? That is when we need the full adder, which I show in Figure 11.19. I am using the same trick I used before. Yes, I could show you the structure of the full adder using CMOS or logic modules, but I can more easily create a full adder by using two Half Adders and an OR module. Note first that the full adder has three inputs, the two digits X and Y, and the carry‐on digit from a previous operation, C*. The first Half Adder is exactly the same as the adder I explained in Figure 11.18...
eBook - ePubMicroprocessor and Microcontroller Interview Questions:: A complete question bank with real-time examples
A complete question bank with real-time examples
- Anita Gehlot(Author)
- 2020(Publication Date)
- BPB Publications(Publisher)
...A Half Adder performs the addition of two inputs, and it produces two outputs namely sum and carry. In the truth table, A and B is termed as inputs while the outputs sum and carry are named as S and C respectively. Block diagram: Circuit diagram: Truth table: Input Output A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 Boolean expression: Sum = A’B + AB’ Carry = AB Full Adder Full adder performs addition operation when the augend and addend number contain more than 2 digits. The carry obtained from the addition of 2 bits is added to the next higher pair of significant bits. Here, the addition operation involves 3 bits, which are augend bit, addend bit and carry bit respectively. The outputs of the full adder are also referred as sum and carry. Block diagram: Circuit diagram: Truth Table: Input Output A B X S C 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Encoder and Decoder Encoder An encoder is a combinational circuit that converts binary information in the form of a 2N input lines. into N output lines, which represent N bit code for the input. For simple encoders, it is assumed that only one input line is active at a time. Decoder Decoders are digital ICs which are used for decoding. In other words, the decoders decrypt or obtain the actual data from the received code, i.e. convert the binary input at its input to a form, which is reflected at its output. It consists of n input lines and 2^n output lines. A decoder can be used to obtain the required data from the code or can also be used for obtaining the parallel data from the serial data received. Multiplexer and Demultiplexer Multiplexer Multiplexer means many into one. A multiplexer is a circuit used to select and route any one of the several input signals to a signal output. A simple example of a non-electronic circuit of a multiplexer is a single pole multi position switch. Multi-position switches are widely used in many electronics circuits...
eBook - ePub- Brian Holdsworth, Clive Woods(Authors)
- 2002(Publication Date)
- Newnes(Publisher)
...In the sum shown in Figure 12.1(a), a carry is generated in the least significant column and is then added in at the second stage where a further carry is generated. The carry has rippled through two stages of the addition. Carry ripple, through many stages, in adder circuits generates unacceptable delays, and methods are now available to eliminate this problem. Figure 12.1 (a) Binary addition. The Half Adder is used for adding together the two least significant bits (dotted) (b) The addition of the four possible combinations of two binary digits A and B (with a carry to the next most significant stage of addition) (c) Truth table for the Half Adder (d) NAND implementation of the Half Adder (e) NOR implementation of the Half Adder The additions shown in Figure 12.1(b) are tabulated in the truth table (see Figure 12.1(c)). The columns headed A and B display every combination of the two binary digits to be added, while the third and fourth columns are the corresponding tabulations of the sum S and carry C, respectively. The Boolean equations for the sum and carry read directly from the truth table are: The implementation of the sum and carry functions using NAND and NOR logic is illustrated in Figure 12.1(d) and 12.1(e). 12.3 The full adder When adding any pair of digits other than the least two significant digits a full adder is required. The full adder circuit has three inputs and two outputs which are shown in the block diagram (see Figure 12.2(a))...
- Ed Lipiansky(Author)
- 2012(Publication Date)
- Wiley-IEEE Press(Publisher)
...The full-adder (FA) receives three input bits: augend (A), addend (B), and carry in (C in), and it produces the sum bit of all three input bits and a carry out (C out) bit. Table 8.13 depicts the truth table for a half-adder. Table 8.13 Half-adder truth table We obtain a maximally SOP form for output bits C out and S of our half-adder. Without doing an explicit 2 -variable K. map it can be seen that: (8.18) and (8.19) The logic implementation for the HA is given by Figure 8.18. Figure 8.18 Half-adder logic implementation. Table 8.14 depicts the truth table of a full-adder. Table 8.14 Full-adder truth table Using a 3- variable K. map we find simplified logic equations to express the sum bit S and C out of the FA. Figure 8.19 depicts the K. maps to obtain the maximally simplified SOP form for output bits C out and S. From the truth table (Table 8.14) we fill in the K. maps for both output bits, C out and S, these are depicted in Figure 8.19. Figure 8.19 (a) Full-adder: K. map for C out ; (b) full-adder: K. map for S. Referring to Figure 8.19 a it is evident that none of the minterms m 1, m 2, m 4, and m 7 has any adjacent minterms. So the simplified SOP and the canonical SOP forms are identical. Moreover, from the canonical equation: (8.20) and since a two-variable XOR is: (8.21) Equation (8.21) is found to be logically equivalent to Equation (8.23) after some Boolean algebra manipulations; that is: (8.22) The simplified SOP form for output bit C out is: (8.23) Writing the canonical form of Equation (8.23) by inspection of Figure 8.19 b we obtain: (8.24) Grouping terms: (8.25) Applying Equation (8.25) to Boolean algebra rules yields: (8.26) The C out of the FA has two alternate logic Equations (8.23) and (8.26). The logic implementations of our full-adder S and C out output bits are depicted in Figure 8.20. Figure 8.20 (a) FA logic implementation of its S output; (b) FA logic implementation of...
eBook - ePub- J. Crowe, Barrie Hayes-Gill(Authors)
- 1998(Publication Date)
- Butterworth-Heinemann(Publisher)
...What are the outputs? Solution Here the result is 1 carry 1, that is S= 1 and C out = 1. (In decimal 1 + 1 + 1 (carry-in) = 3; in binary 01+01 + 1 (carry-in) = 11.) Using the Karnaugh maps to obtain minimised expressions for S and C out, we notice the chequerboard pattern of an XOR gate in the sum term to give: whilst The circuit to implement the full adder is shown in Fig. 4.13. Fig. 4.13 Circuit diagram of a full adder 4.2 COMBINATIONAL LOGIC DESIGN EXAMPLE: A FOUR-BIT ADDER In this section we consider the design of a four-bit adder; i.e. a circuit that adds together two four-bit binary numbers. This needs to be a combinational logic circuit and therefore serves as a useful exercise to apply what we have learnt. To recap, we know that any truth table can be implemented using a product of sums or sum of products expression in either a fundamental or minimised (via Boolean algebra or Karnaugh maps for example) form. Using this approach we end up with a two-level circuit implementation of AND-OR, OR-AND, NAND-NAND or NOR-NOR. We have not yet considered the practicalities of any circuits we have designed or analysed, which is one of the purposes of this section. We begin by looking again at both the benefits and problems of two-level circuits, before considering this means of implementation for the four-bit adder. We then move on to two other methods of implementation which rely upon a more thorough look at what we want the circuit to do, rather than simply treating it as a combinational logic problem to be approached using fixed ‘rules’. 4.2.1 Two-level circuits Two-level circuits are direct implementations of sum of products and product of sums forms, either in fundamental form (straight from the truth table) or after minimisation...
eBook - ePub- M. Michael Vai(Author)
- 2017(Publication Date)
- CRC Press(Publisher)
...The basic element available for building an adder is a full adder. Fig. 7.1 shows that a one-bit full adder accepts two 1-bit operands (a i, b i) and one carry-in bit (c i −1) and produces a result consisting of 1 sum bit (s i) and 1 carry-out bit (c i). An alternative view of the one-bit full adder is that it accepts three 1-bit operands and produces a two-bit sum. Fig. 7.1 One-bit full-adder. A number of one-bit full adders can be cascaded to form a ripple-carry adder (see Fig. 7.2). The ripple-carry adder is extremely modular since it contains only one-bit full adders. The structure is also very regular. All full adders in the ripple-carry adder are connected to their neighbors in the same way. The interconnections within the ripple-carry adder are limited to between neighboring full adders. The full adder cell can be laid out to accept a carry-in bit (c i −1) from its right edge and produces a carry-out bit (c i) at its left edge. This layout will facilitate the use of tessellation to the design of a ripple-carry adder. Fig. 7.3 illustrates that when two full adder cells are placed side by side, their power rails (V DD and V SS) as well as their carry paths are connected. It is also quite simple to expand a ripple-carry adder. An n -bit ripple-carry adder can be expanded to accept (n + m)-bit operands by incorporating m additional full-adder cells. Fig. 7.2 Ripple carry adder. Fig. 7.3 Full adder tessellation. A ripple-carry adder has a computation time that is proportional to the number of bits in its operands. The wider the operands, the longer does it take the ripple-carry adder to complete its addition. Whether this presents a limitation or not on the use of a ripple-carry adder naturally depends on the application on hand...
eBook - ePub- John Stonham(Author)
- 2017(Publication Date)
- CRC Press(Publisher)
...If bit b i, of the multiplier is 0 2 then the multiplication A × b i must be zero for all possible values of A. If b i is 1 2 then the multiplication A × b i is equal to A. Therefore no extra logical operation or calculation is required in this step of the algorithm. Binary multiplication is therefore only a series of shift-and-add operations and like the subtractor operation, this too can be implemented based on an adder circuit, enhanced with three data stores and a control unit. A block diagram of a binary multiplier is shown in Fig. 7.7. Fig. 7.7 A binary shift-and-add multiplier. For example, parallel or look-ahead-carry adder. The binary adder is the main processor in a multiplier. It can be a ripple-through-carry type or one of the faster adders previously described. The adder resolution needs to be 2 n bits as the data in register A (the multiplicand) and register B (the multiplier) are n bits. Owing to the increased complexity of the system, a controller unit is necessary to schedule the flow of information. The controller receives the least significant bit b 0 from register B via its input K. If b 0 is 0, register A is shifted 1 bit left initiated by control signal C 2 and register B is shifted 1 bit right through C 3. If, however, b 0 is 1 then the contents of register A and the accumulator are input to the adder via controls C 1 and C 4 and the resulting addition stored in the accumulator before the shift controls are applied to registers A and B...
eBook - ePubDigital Design
Basic Concepts and Principles
- Mohammad A. Karim, Xinghao Chen(Authors)
- 2017(Publication Date)
- CRC Press(Publisher)
...The resultant sum is stored in a memory device (often in a register made up of several cascaded flip-flops), and the carry-out is stored in a flip-flop and then fed back into the single-bit full adder as carry-in input for the next cycle of addition. This transmission addition storage process is repeated until all of the bits have been processed. The final sum would consist of the last carry-out (the most significant bit) and the remaining sum bits stored in the register. The characteristics of the registers and how the inputs are fed sequentially to the adder will be considered in Chapters 9 and 10. For the time being it is enough to understand that the registers in question are capable moving stored bits from left to the right. Sequential systems are not devoid of problems. Some of these problems often are very critical to the functioning of the system and thus must be considered very carefully. Consider the logic circuit shown in Figure 7.63. When the input is a 0, the output becomes a 1. Since the output in turn is fed back as a input, the values of the output disagree with that of the input resulting in an indeterminate feedback system. Such problems are avoided by eliminating the conditions of continuous oscillations. Figure 7.62 A serial addition circuit. Figure 7.63 An indeterminate logic circuit. Figure 7.64 (a) Combinatorial circuit and (b) its corresponding timing diagram. To comprehend another frequently encountered problem, consider next the combinatorial logic circuit shown in Figure 7.64 a where the gates numbered 1, 2, and 3, respectively, have gate delays of Δ t 1, Δ t 2, and Δ t 3. We arbitrarily chose that at time t 0 all three inputs are 1 and at time t > t 0 the input A, for example, changes from a 1 to a 0. Figure 7.64 b shows the resulting timing diagram provided that Δ t 1 < Δ t 2. It is apparent that the combinatorial circuit output results in a transient error pulse for a period given by Δ t 2 – Δ t 1...
