Program Counter
The program counter is a register in a computer processor that stores the memory address of the next instruction to be executed. It keeps track of the current position in the program's sequence of instructions, allowing the processor to fetch the next instruction from memory and execute it. The program counter is a crucial component in the control flow of a computer program.
5 Key excerpts on "Program Counter"
- Mohamed Rafiquzzaman(Author)
- 2021(Publication Date)
- CRC Press(Publisher)
...The 32-bit microprocessors include special on-chip combinational network called the Barrel Shifter. The PC normally contains the address of the next instruction to be executed. Upon activating the microprocessor chip’s RESET input, the PC is normally initialized with the address of the first instruction. For example, the 80486, upon hardware reset, reads the first instruction from the 32-bit address FFFFFFF0 16. In order to execute the instruction, the microprocessor normally places the PC contents on the address bus and reads (fetches) the first instruction from external memory. The Program Counter contents are then automatically incremented by the ALU. The microcomputer thus executes a program sequentially unless it encounters a jump or branch instruction. The size of the PC varies from one microprocessor to another depending on the address size. For example, the 68000 has a 24-bit PC, while the 68040 contains a 32-bit PC. The instruction register (IR) contains the instruction to be executed. After fetching an instruction from memory, the microprocessor places it in the IR for translation. The status register contains individual bits with each bit having a special meaning. The bits in the status register are called flags. Each flag is usually set or reset by an ALU operation. The flags are used by the Conditional Branch instructions. Typical flags include carry, sign, zero, and overflow. The carry (C) flag is used to reflect whether or not an arithmetic operation such as ADD generates a carry. The carry is generated out of the 8th bit (bit 7) for byte operations, 16th bit (bit 15) for 16-bit, or 32nd bit (bit 31) for 32-bit operations. The carry is used as the borrow flag for subtraction. In multiple word arithmetic operations, any carry from a low-order word must be reflected in the high-order word for correct results. The zero (Z) flag is used to indicate whether the result of an arithmetic or logic operation is zero...
- Ed Lipiansky(Author)
- 2012(Publication Date)
- Wiley-IEEE Press(Publisher)
...Upon a jump or branch instruction the PC wants to be loaded with a new destination or jump-to address. Such address, called address X, is fetched from memory along with the four-bit opcode. Once the PC gets loaded with this destination address X the jump will always fetch the next instruction from this new destination address. In the case of the BRNA (branch on negative accumulator) the branching will occur if the condition of a negative accumulator (S flag set) was met before the BRNA instruction. If the branch condition is met the next instruction fetch takes place from the destination address X. If the branch condition is false the branch does not occur and the PC remains loaded with the address of the previous instruction incremented by one. From all of the above we need to have the PC perform at least three distinct functions: hold its contents, auto-increment by one or get loaded with a new destination address. Additionally the PC will have an asynchronous Reset input line to ensure that its contents are cleared upon power-up reset. Because of all of that functionality the PC is a little more involved that the accumulator A, MAR or MBR registers. One way of implementing the PC is with a counter, to obtain the auto-increment feature. The PC could use the CPU ALU to increment its contents by one, but this is not desirable because the PC would be using the ALU, which is a valuable resource of the CPU. Figure 10.5 depicts an implementation of the PC. Table 10.4 describes all the operations that the PC performs. Note that the PC implementation in itself is a simple synchronous state machine. Its basic functions are: (1) hold, (2) increment by one, (3) external data synchronous load, and (4) synchronous reset (or clear)...
eBook - ePubElectronics Explained
The New Systems Approach to Learning Electronics
- Louis E. Frenzel(Author)
- 2010(Publication Date)
- Newnes(Publisher)
...Such multiple registers simplify, speed up, and shorten a program to perform a given operation. Some sophisticated CPUs have 4, 8, 16, or even more accumulators. Usually they are referred to as GPRs or a register file. These registers can each use the ALU and act as temporary storage locations for data and the intermediate results of calculations. Instructions are provided to move data from one register to another. FIGURE 6.6 How ALU adds or otherwise processes two data values. In most micros, the GPRs share a single ALU. The ALU accepts only two input words and generates a single output word. The two words to be processed by the ALU usually come from any two GPRs or any GPR and a designated memory location. The destination of the ALU output can also be one of the GPRs in some CPUs. Control unit CPUs also have several other registers, including the instruction register; the Program Counter, also called the instruction counter; and the memory address register, also called the address buffer. The instruction register (IR) is used to store the instruction word. When the CPU fetches an instruction from memory, it is temporarily stored in the IR. The instruction is a binary word or code that defines a specific operation to be performed. The instruction word is also called the op code or operation code. The CPU decodes the instruction, and then executes it. The Program Counter (PC) is really a counter and a register. It stores a binary word that is used as the address for accessing the instructions in a program. If a program begins with an instruction stored in memory location 43, the PC is first loaded with the address 43. The address in the PC is applied to the memory, causing the instruction in location 43 to be fetched and executed. After the instruction is executed, the PC is incremented (add 1) to the next address in sequence, or 44...
eBook - ePub- J S Anderson(Author)
- 2012(Publication Date)
- Routledge(Publisher)
...If you haven't then we have what is called a program ‘bug’. The computer only does what you tell it to do, not what you think you've told it to do – but don't worry! – generally, it is a relatively simple process to write programs that will run satisfactorily; it only takes practice. The box labelled ‘Fetch (2)’ shows what happens next in the sequence. The PC is now at 5C01H, the IR still contains 3AH and the accumulator has been loaded with 15H. The PC then increments ready to point to the next memory location (5C02H) and look at the next instruction. The fetch-execute sequence continues in this way until all the instructions in the program have been fetched and executed. Illustrating the fetch-execute cycle Now that the fetch-execute cycle has been explained, let's try a few examples. To illustrate the cycle, we now modify the method of representing it so that it looks like Figure 7.5. To make the layout simpler and more understandable we now write the PC value at the top of the box; inside the box we put the contents of the IR and any other registers that are involved in the operation. All the registers to be used should be listed from the beginning and be labelled ‘XX’ (meaning contents unknown) to show that the contents have not yet been modified by program execution. The incremented PC value is placed at the bottom of the register list even though it is usually incremented after an instruction or piece of data is fetched, and before it's executed. Remember, after execution, the CPU looks at the PC for the next memory location and fetches from it. Figure 7.5 Illustrating the changing register contents during the fetch-execute cycle – first example. In Figure 7.5 we see that the PC initially points to location 5C00H. The CPU looks into that location and discovers the code 3AH there. This code is copied into the instruction register...
eBook - ePubProgramming 8-bit PIC Microcontrollers in C
with Interactive Hardware Simulation
- Martin P. Bates(Author)
- 2008(Publication Date)
- Newnes(Publisher)
...The CPU has one main working register (W), through which all the data must pass. If a branch instruction (conditional jump) is decoded, a bit test is carried out; and if the result is true, the destination address included in the instruction is loaded into the Program Counter to force the jump. If the result is false, the execution sequence continues unchanged. In assembly language, when CALL and RETURN are used to implement subroutines, a similar process occurs. The stack is used to store return addresses, so that the program can return automatically to the original program position. However, this mechanism is not used by the CCS C compiler, as it limits the number of levels of subroutine (or C functions) to eight, which is the depth of the stack. Instead, a simple GOTO instruction is used for function calls and returns, with the return address computed by the compiler. Figure 1.3: PIC16F877 MCU Block Diagram Table 1.1: PIC16F877 Simplified File Register Map RAM File Registers The main RAM block (Table 1.1) is a set of 368 8-bit file registers, including the special function registers (SFRs), which have a dedicated function, and the general purpose registers (GPRs). When variables are created in C, they are stored in the GPRs, starting at address 0020h. The file registers are divided into four blocks, register banks 0 to 3. The SFRs are located at the low addresses in each RAM bank. Some registers are addressable across the bank boundaries; for example, the status register can be accessed in all blocks at the corresponding address in each bank. Others are addressable in only a specific page, for example, Port A data register. Some register addresses are not physically implemented. Since some registers are accessible in multiple banks, bank switching can be minimized by the compiler when assembling the machine code, thus saving program code space and execution time...
