FPGA Prototyping by SystemVerilog Examples

Xilinx MicroBlaze MCS SoC Edition

Pong P. Chu

• Éditeur: Wiley
• Année: 2018
• ISBN:
  9781119282709
• Édition: 2
• Sujet: Technology & Engineering
• Sous-sujet: Electrical Engineering & Telecommunications

A hands-on introduction to FPGA prototyping and SoC design

This is the successor edition of the popular FPGA Prototyping by Verilog Examples text. It follows the same "learning-by-doing" approach to teach the fundamentals and practices of HDL synthesis and FPGA prototyping. The new edition uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow the strict design guidelines and coding practices used for large, complex digital systems.

The book is completely updated and uses the SystemVerilog language, which "absorbs" the Verilog language. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software "programmability" and develop complex and interesting embedded system projects. The new edition:

• Adds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I 2 C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.
• Introduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelope generator.
• Expands the original video controller into a complete stream based video subsystem that incorporates a video synchronization circuit, a test-pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer.
• Provides a detailed discussion on blocking and nonblocking statements and coding styles.
• Describes basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor.
• Provides an overview of bus interconnect and interface circuit.
• Presents basic embedded system software development.
• Suggests additional modules and peripherals for interesting and challenging projects.

FPGA Prototyping by SystemVerilog Examples makes a natural companion text for introductory and advanced digital design courses and embedded system courses. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest.

PART I
BASIC DIGITAL CIRCUITS DEVELOPMENT

CHAPTER 1
GATE-LEVEL COMBINATIONAL CIRCUIT

HDL (hardware description language) is used to describe and model digital systems. SystemVerilog is one of the major HDLs. In this chapter, we use a simple comparator to illustrate the skeleton of a SystemVerilog program. The description uses only logical operators and represents a gate-level combinational circuit, which is composed of simple logic gates. In Chapter 3, we cover the remaining operators and constructs and examine the register-transfer-level combinational circuits, which are composed of intermediate-sized components, such as adders, comparators, and multiplexers.

1.1 INTRODUCTION

1.1.1 Brief history of Verilog and SystemVerilog

Verilog is a hardware description language. It was developed in the mid-1980s and later transferred to the IEEE (Institute of Electrical and Electronics Engineers). The language is formally defined by IEEE Standard 1364 and the document is known as the LRM (Language Reference Manual). The standard was ratified in 1995 (known as Verilog-1995) and significantly revised in 2001 (known as Verilog2001). A further revision, which contains a few minor changes, was published in 2005. Unless otherwise specified, the term “Verilog” used in the book is referred to Verilog-2001.

Verilog was developed for gate-level and register-transfer-level design and modeling and it did not include advanced high-level verification features, such as assertions, functional coverage, and constrained random testing. SystemVerilog first served as an extension of Verilog that supports the verification features. The extension was ratified by IEEE in 2005 and formally defined by IEEE Standard 1800. It is referred to as SystemVerilog-2005.

In 2009, Verilog and SystemVerilog were combined into a single standard and defined by IEEE Standard 1800. The merged languages are called SystemVerilog and referred to as SystemVerilog-2009. The merge and name selection implies that Verilog is now part of SystemVerilog and the Verilog language has ceased to exist.

The merge and naming scheme may cause some confusion. SystemVerilog-2005 is a pure hardware verification language but the newer SystemVerilog (SystemVerilog-2009 and beyond) is a hardware description and verification language that incorporates both design and verification features into a single framework.

Unless otherwise specified, the term “SystemVerilog” used in the book is referred to SystemVerilog-2009, which includes hardware description portion and is a “superset” of the original Verilog.

1.1.2 Book coverage

SystemVerilog is an extremely complex language. Only a small subset of the language constructs is intended to describe gate-level and register-transfer-level systems and even a smaller subset can be recognized by the synthesis software tool and transformed into physical hardware.

The focus of this book is on hardware design rather than on the language. We introduce the key SystemVerilog synthesis constructs by examining a collection of examples. Although the syntax of SystemVerilog is somewhat like that of the C language, its semantics (i.e., “meaning”) is based on concurrent hardware operation and is totally different from the sequential execution of C. The subtlety of some language constructs and certain inherent nondeterministic behavior of SystemVerilog can lead to difficult-to-detect errors and can introduce a discrepancy between simulation and synthesis. The coding of this book follows a “better-safe-than-buggy” philosophy. Instead of writing quick and short codes, the focus is o...

Table des matières

• Cover
• Titlepage
• Copyright
• Preface
• Acknowledgments
• PART I: BASIC DIGITAL CIRCUITS DEVELOPMENT
• PART II: EMBEDDED SOC I: VANILLA FPRO SYSTEM
• PART III: EMBEDDED SOC II: BASIC I/O CORES
• PART IV: EMBEDDED SOC III: VIDEO CORES
• PART V: EPILOGUE
• INDEX
• EULA