RISC Processor
A RISC (Reduced Instruction Set Computer) processor is a type of microprocessor that emphasizes a small, highly optimized set of instructions, which allows it to execute simple instructions in a single clock cycle. This design approach aims to improve performance by simplifying the processor's instruction set and focusing on executing instructions quickly. RISC processors are commonly used in embedded systems and mobile devices.
6 Key excerpts on "RISC Processor"
eBook - ePub- Jerry C. Whitaker(Author)
- 2018(Publication Date)
- CRC Press(Publisher)
...In Complex instruction set computer (CISC) microprocessors, small register sets, memory to memory operations, large instruction sets (with variable instruction lengths), and the use of microcode are typical. The basic simplified philosophy of the CISC microprocessor is that added hardware can result in an overall increase in speed. The penultimate CISC processor would have each high-level language statement mapped to a single native CPU instruction. Microcode simplifies the complexity somewhat but necessitates the use of multiple machine cycles to execute a single CISC instruction. After the instruction is decoded on a CISC machine, the actual implementation may require 10 or 12 machine cycles depending on the instruction and addressing mode used. The original trend in microprocessor development was toward increased complexity of the instruction set. Although there may be hundreds of native machine instructions, only a handful are actually used. Ironically, the CISC instruction set complexity evolves at a sacrifice in speed because its harder to increase the clock speed of a complex chip. Recently, recognition of this along with demands for increased clock speeds have yielded favor toward the reduced instruction set (RISC) microprocessor. This trend reversal followed studies in the early 1970s that showed that although the CISC machines had plenty of instructions, only relatively few of these were actually being used by programmers. In fact, 85% of all programming consists of simple assignment instructions) (i.e., A=B). RISC machines have very few instructions and few machine cycles to implement them. What they do have is a lot of registers and a lot of parallelism. The ideal RISC machine attempts to accomplish a complete instruction in a single machine cycle. If this were the case, a 100-MHz microprocessor would execute 100 million instructions per second. There are typically many registers for moving data to accomplish the goal of reduced machine cycles...
- Mohamed Rafiquzzaman(Author)
- 2021(Publication Date)
- CRC Press(Publisher)
...Both Intel and Motorola introduced 32-bit RISC (Reduced Instruction Set Computer) microprocessors, namely the Intel 80960 and Motorola MC88100/PowerPC with simplified instruction sets. Note that the purpose of RISC microprocessors is to maximize speed by reducing clock cycles per instruction. Almost all computations can be obtained from a simple instruction set. RISC microprocessors have hardwired instruction sets like the non-RISC microprocessors such as the Intel 8085 and MOS 6502. This means that for every instruction, there exists actual, physical connections that provide the desired instruction decoding. The microprocessor, therefore, does not use valuable clock cycles (machine cycles) in instruction decoding. Most RISC instructions require a maximum of only two clock cycles to complete. These instructions are restricted to register-to-register operations with load and store for memory access. Since RISC-type microprocessors are hardwired, instructions may be executed simultaneously (as long as the instructions do not share the same register.) This technique is known as pipelining. Pipelining is the mechanism that actually enables simultaneous processing to occur. Instructions are fetched in sequential order. The processor continues to fetch instructions even though it has not executed the present instruction. This provides an input pipeline to the instruction cache. At this stage, the instructions are intelligently fed into the instruction execution unit for processing. When an instruction is executed, the registers used by the instruction clear respective bits in a scoreboard register. As the microprocessor is executing a given instruction, it checks the scoreboard register to see if the next instructions (residing in a fast read/write memory internal to the microprocessor called the instruction cache) use registers that are currently in use. Instructions not using the same registers can therefore be executed at the same time...
eBook - ePub- William J. Martin(Author)
- 2017(Publication Date)
- Routledge(Publisher)
...The convergence between the enabling technologies has progressed to such effect that even for purposes of exposition, it is difficult to separate out one technology from another. COMPUTER HARDWARE Dramatic advances in hardware have been responsible for the continued expansion of computers into our daily lives and for making many of the software advances practical. Even more exciting prospects beckon with the development of new hardware architectures and networking concepts like RISC (Reduced Instruction Set Computing), parallel processors and neural computers, and image processing. Microprocessor technology The microchip remains central to progress in the information and communication technologies. Silicon continues to provide the main raw material for both logic chips and memory chips, known today as Dynamic Random Access Chips (DRAMS). The cost-performance ratio which gained such astonishing momentum during the 1960s, has continued in a positive direction, delivering prodigious increases in the amount of computing power available at greatly reduced cost. Very advanced chips would feature several processors, some of reduced instruction set (RISC) design, and would have processing speeds in excess of 100 million instructions per second (MIPS). There are two major categories of microprocessor technology: the traditional CISC (Complex Instruction Set Computing) and the more recent microprocessors based on RISC (Reduced Instruction Set Computing). The more instructions contained in a central processing unit (CPU) instruction set and the more complicated those instructions, the more clock cycles the CPU needs to complete an instruction search. Traditional CISC technology has complex sets of between 150 and 300 instructions and processes only one instruction search at a time. The higher-performance RISC chips, on the other hand, contain perhaps 70 to 80 of only the most frequently used instructions...
- Ed Lipiansky(Author)
- 2012(Publication Date)
- Wiley-IEEE Press(Publisher)
...From a computer architecture point of view our design is closer to a von Neumann machine. This is an architecture that consists of a stored-program digital machine that has a central processing unit and a single separate memory unit that holds program instructions as well as data. An example of a RISC and CISC is covered in References 3, 4, and 6 in the Further Reading section. The instruction set architecture (ISA) that our simple CPU supports consists of a few but very significant instructions that all real-world machines support. The purpose of studying a very simple CPU is to prove basic architecture concepts to the reader, which later on we will use to add real world factors that embedded systems face. Such factors over and above the computer architecture are timing analysis of the CPU, how to clock the machine, the reset logic, and integrated circuit power decoupling. The basic instructions that our simple CPU supports are: LOAD, STORE, AND, ADD, (unconditional jump) JMP, (conditional branch) BRNA, and (complement) CMPA. Our CPU has a single accumulator register or simply register A. Register A is a 16-bit wide register. The computer memory has 4096 16-bit wide words, that is, 4K words. Since the memory has 4K memory locations, the address width required to address each word uniquely, is 12 since 2 12 is 4096. The program counter register or the PC is 12 bits wide and it is used to store the address of the instruction to be executed immediately after the currently being executed instruction. Summarizing our CPU has 16 -bit wide data paths between register A and its memory. All memory accesses are done with a 12-bit wide address. The PC stores the address of the to-be executed instruction. Our simple CPU has a single 16-bit word instruction word. The lower 12 bits are used as an address to memory for those instructions that require such address, while the upper four bits are allocated as operational code bits (opcode bits) format...
eBook - ePub- Wai-Kai Chen, Wai-Kai Chen(Authors)
- 2003(Publication Date)
- CRC Press(Publisher)
...RISC concepts allow the microarchitecture design of machines to be more easily pipelined, reducing the processor clock cycle frequency and the overall speed of a machine. The RISC concept resulted from improvements in programming languages, compiler technology, and memory size. The HP PARISC, Sun SPARC, IBM Power PC, MIPS, and DEC Alpha machines are examples of RISC architectures. Architecture models allowing multiple instructions to issue in a clock cycle are very long instruction word (VLIW). VLIWs issue a fixed number of operations conveyed as a single long instruction and place the responsibility of creating the parallel instruction packet on the compiler. EarlyVLIW processors suffered from code expansion due to instructions. Examples of VLIW technology are the Multiflow Trace and Cydrome Cydra machines. Explicitly parallel instruction computing (EPIC) is similar in concept to VLIW in that both use the compiler to explicitly group instructions for parallel execution. In fact, many of the ideas for EPIC architectures come from previous RISC and VLIW machines. In general, the EPIC concept solves the excessive code expansion and scalability problems associated with VLIW models by not completely eliminating its functionality. Also, the trend of compiler-controlled architecture mechanisms are generally considered part of the EPIC-style architecture domain. The Intel IA-64, Philips Trimedia, and Texas Instruments ‘C6X are examples of EPIC machines. 11.5 Instruction-Level Parallelism Modern processors are being designed with the ability to execute many parallel operations at the instruction level. Such processors are said to exploit instruction-level parallelism (ILP)...
eBook - ePubEmbedded Systems
Hardware, Design and Implementation
- Krzysztof Iniewski(Author)
- 2012(Publication Date)
- Wiley(Publisher)
...Therefore, embedded systems are employing multicore architecture more and more. The multicore is good for multiplying single-core performance with maintaining the core efficiency, but does not enhance the efficiency of the core itself. Therefore, we must use highly efficient cores. SuperH ™ (Renesas Electronics, Tokyo) reduced instruction set computer (RISC) engine family (SH) processor cores are highly efficient typical embedded central processing unit (CPU) cores for both single- and multicore chips. 1.2.1 History of SH Processor Cores Since the beginning of the microprocessor history, a processor especially for PC/servers had continuously advanced its performance while maintaining a price range from hundreds to thousands of dollars [11, 12]. On the other hand, a single-chip microcontroller had continuously reduced its price, resulting in the range from dozens of cents to several dollars with maintaining its performance, and had been equipped to various products [13]. As a result, there was a situation of no demand on the processor of the middle price range from tens to hundreds of dollars. However, with the introduction of the home game console in the late 1980s and the digitization of the home electronic appliances from the 1990s, there occurred the demands to a processor suitable for multimedia processing in this price range. Instead of seeking high performance, such a processor has attached great importance to high efficiency. For example, the performance is 1/10 of a processor for PCs, but the price is 1/100, or the performance equals to a processor for PCs for the important function of the product, but the price is 1/10. The improvement of area efficiency has become the important issue in such a processor. In the late 1990s, a high performance processor consumed too high power for mobile devices, such as cellular phones and digital cameras, and the demand was increasing on the processor with higher performance and lower power for multimedia processing...
