Multicore Technology

Architecture, Reconfiguration, and Modeling

Muhammad Yasir Qadri, Stephen J. Sangwine

• Publisher: CRC Press
• Year: 2018
• ISBN:
  9781351832731
• Edition: 1
• Topic: Computer Science
• Subtopic: Computer Engineering
• Index: Computer Science

The saturation of design complexity and clock frequencies for single-core processors has resulted in the emergence of multicore architectures as an alternative design paradigm. Nowadays, multicore/multithreaded computing systems are not only a de-facto standard for high-end applications, they are also gaining popularity in the field of embedded computing.

The start of the multicore era has altered the concepts relating to almost all of the areas of computer architecture design, including core design, memory management, thread scheduling, application support, inter-processor communication, debugging, and power management. This book gives readers a holistic overview of the field and guides them to further avenues of research by covering the state of the art in this area. It includes contributions from industry as well as academia.

Part V

Networks-on-Chip

10

On Chip Interconnects for Multicore Architectures

Prasun Ghosal

Department of Information Technology, Bengal Engineering and Science University, Shibpur, India

Soumyajit Poddar

School of VLSI Technology, Bengal Engineering and Science University, Shibpur, India

CONTENTS

10.1 Introduction

10.2 Evolution of Interconnects for Multicore Architectures

10.2.1 More than Moore Trends: A New Perspective

10.2.2 From Single Bus Based to Network-on-Chip Architectures

10.2.3 On Chip Applications

10.3 Emerging Technologies for Interconnections

10.3.1 Three Dimensional Interconnects

10.3.2 Photonic Interconnects

10.3.3 Wireless Interconnect Technology

10.3.4 RF Waveguide Interconnects

10.3.5 Carbon Nanotubes (CNT)

10.4 Conclusion and Future Research Directions

10.1 Introduction

How do we exploit current technology to harness the full power of parallel computing architectures within the constraints of minimum energy, die-area, and complexity? Finding a viable answer to the above question needs a paradigm shift from the 1990s philosophy that a better processor has a functionally better and faster arithmetic logic unit (ALU) than its predecessor. Today’s process technologies are producing transistors in the Deep Sub-Micron (DSM) regime. These devices operate at GHz (gigahertz) frequencies at pico Watt power levels. Using these devices, it is possible to integrate several different types of functionalities into the processor itself. Also, Moore’s Law has been followed quite well over the past few years. However, the current level of progress has reached a communication bottleneck in terms of interconnect and intra-chip communication resources. The latter problem is solved by putting emphasis on designing a reliable and efficient Network-on-Chip (NoC). Interconnects using metal wires have several issues for distributing both signals and clocks across the chip, e.g., power consumption of wires and use of repeaters. The remainder of this chapter discusses, from a communication viewpoint, the role of current and future interconnects used in multicore architectures.

10.2 Evolution of Interconnects for Multicore Architectures

There are various driving forces behind today’s growth of the semiconductor industry. One of these forces is the continuing demand from the electronics and embedded market to pack more and more devices onto the same chip. According to Moore’s Law, the number of components that can be incorporated per integrated circuit increases exponentially over time (Moore 1998). As the component count increases per chip, so does the connection infrastructure. At least, for the last decade, scaling down transistor size went hand-in-hand with scaling down of wire width. However, there is a limit to the minimum width a metal wire can be scaled down, below which fringing effects are exacerbated.

Interconnects provide two important functions, namely, supply rails and signal lines. Supply rails carry DC and signal lines carry AC (for digital circuits) or varying DC (for mixed signal circuits). In addition, for digital circuits, clock lines need careful design to minimize clock skew. Maintaining global synchrony is an important issue for multicore chips designed today. Providing a global clock signal across the chip is difficult due to the capacitance of such a network and its complexity (which is further increased by gated clocks). Applications such as multimedia and communication demand heterogeneous cores to be placed on the same chip. These cores may not be regular in physical size and/or function. This would cause the interconnect infrastructure also to be heterogeneous.

Mainly, wires are classified into three groups, based on their length. They are the local (short), intermediate (medium), and global (long) wires. According to The International Technology Roadmap for Semiconductors 2009 for Interconnects (2009), signal delay time for local wires is typically much smaller than a clock cycle and decreases with scaling for technology nodes greater than 45 nm. Below 45 nm, gate delay begins to dominate the local wire delay and offsets scaling benefits. The delay for intermediate wires will grow only slightly with technology scaling.

FIGURE 10.1
Side view of multipath interconnect

The global wire delay increases with scaling due to the increased resistance and increased length (capacitance and inductance effects). The power distribution network for the chip needs very low resistance global wires, mainly due to the low values of the supply voltage and high values of current. Alternate packaging techniques such as ball grid array are used to distribute the power across the chip and eliminate lateral power feeds that face voltage drop problems. In the absence of repeaters, a global wire suffers from a delay proportional to the square of its wire length. For this reason, a longer wire is usually broken into several segments (to reduce the delay quadratically), and repeaters are inserted between segments to boost the signal level (Rabaey, Chandrakasan, and Nikolic 2003).

Multipath interconnects are now used for high-performance interconnects carrying high currents. The concept is shown in Figure 10.1. It is a...

Table of contents

• Cover
• Half Title
• Title Page
• Copyright Page
• Table of Contents
• List of Figures
• List of Tables
• Preface
• Editors
• Contributors
• Acronyms
• I Architecture and Design Flow
• II Parallelism and Optimization
• III Memory Systems
• IV Debugging
• V Networks-on-Chip
• Bibliography
• Index