Handbook of Semiconductor Manufacturing Technology

Yoshio Nishi, Robert Doering, Yoshio Nishi, Robert Doering

• Publisher: CRC Press
• Year: 2017
• ISBN:
  9781351829823
• Edition: 2
• Topic: Technology & Engineering
• Subtopic: Electrical Engineering & Telecommunications
• Index: Technology & Engineering

Retaining the comprehensive and in-depth approach that cemented the bestselling first edition's place as a standard reference in the field, the Handbook of Semiconductor Manufacturing Technology, Second Edition features new and updated material that keeps it at the vanguard of today's most dynamic and rapidly growing field. Iconic experts Robert Doering and Yoshio Nishi have again assembled a team of the world's leading specialists in every area of semiconductor manufacturing to provide the most reliable, authoritative, and industry-leading information available.Stay Current with the Latest Technologies
In addition to updates to nearly every existing chapter, this edition features five entirely new contributions on…

• Silicon-on-insulator (SOI) materials and devices
  
• Supercritical CO2 in semiconductor cleaning
  
• Low-? dielectrics
  
• Atomic-layer deposition
  
• Damascene copper electroplating
  
• Effects of terrestrial radiation on integrated circuits (ICs)Reflecting rapid progress in many areas, several chapters were heavily revised and updated, and in some cases, rewritten to reflect rapid advances in such areas as interconnect technologies, gate dielectrics, photomask fabrication, IC packaging, and 300 mm wafer fabrication.While no book can be up-to-the-minute with the advances in the semiconductor field, the Handbook of Semiconductor Manufacturing Technology keeps the most important data, methods, tools, and techniques close at hand.

1
Introduction to Semiconductor Devices

John R. Hauser
North Carolina State University

1.1 Introduction

1.2 Overview of MOS Device Characteristics

1.3 MOSFET Device Scaling

Scaling Rules • Performance of Scaled Devices

1.4 Manufacturing Issues and Challenges

MOSFET Gate Stack Issues • Channel Doping Issues • Source/Drain Contact Issues • Substrate and Isolation Issues • Thermal Budget Issues

1.5 Advanced MOS Device Concepts

SOI Substrates and Devices • Multiple Gate MOS Devices • Transport Enhanced MOS Devices • MOSFETS with Other Semiconductors • Advanced Semiconductor Device Concepts

1.6 Conclusions

References

1.1 Introduction

The silicon metal oxide semiconductor field effect transistor (MOSFET) has emerged as the ubiquitous active element for silicon very large scale integration (VLSI) integrated circuits. The competitive drive for improved performance and cost reduction has resulted in the scaling of circuit elements to ever-smaller dimensions. Within the last 35 years, MOSFET dimensions have shrunk from a gate length of 5 μm in the early 1970s to 45 nm today, and are forecast to reach less than 10 nm at the end of the projected shrink path in about 2020. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020.

In the early days of semiconductor device development (the 1950s), the bipolar junction transistor was the dominant semiconductor device. As large-scale integration of devices developed in the 1960s, the MOSFET became the preferred device type and has eventually grown to dominate the use of semiconductor devices in integrated circuits (ICs). This has been predominantly due to the development of complementary MOS devices (CMOS), where digital logic circuits can be formed that exhibit extremely low power dissipation in either of the two logic states. Complementary MOS is not only a device technology, but also a logic circuit technology that dominates the IC world because of the advantages of very low power dissipation over other forms of semiconductor circuits. Thus, over time in the general scheme of ICs, bipolar semiconductor devices have come to be used in only special applications. Because of this dominance of MOS devices in large-scale ICs, only the MOSFET will be reviewed in this discussion.

In the late 1960s, the semiconductor industry emerged from the era of wet processing, contact printing, and negative resist at approximately 10 μm minimum gate lengths to face considerable problems related to particulate reduction, dry processing, and projection printing. Positive resist overcame the resist-swelling problem and provided improved resolution, but at the cost of particle generation caused by brittle resist and railed wafer handling equipment in use at that time. Whole wafer projection printing improved the resolution and yield, but required the use of larger wafers to offset the additional capital cost. Dry processing was the banner developmental thrust of the period. Plasma processing, initially conducted in a pancake reactor between opposing electrodes dramatically increased yield, but required a trained artisan to achieve uniformity and throughput. Sputter metal deposition replaced evaporation that had earlier produced substrate stress voiding problems. Wafer size was increased to offset the cost of the more sophisticated and expensive process equipment. Dynamic random access memory factories were the workhorses to develop and prove out the next technology generation. The MOSFET began to emerge in the 1970s as the device technology for VLSI, although large-scale integration (LSI) bipolar technology persisted longer than many forecast.

In the early 1980s, Japanese semiconductor manufacturers seized manufacturing technology leadership with major capital commitments, dramatically increasing manufacturing yield and factory efficiency, to capture a major share of the Dynamic random access memories (DRAM) market. Quality became a major issue when it was reported that quality levels of Japanese memories were consistently and substantially better than American manufacturers. As the cost of manufacturing equipment development escalated, a transition began with the emergence of dedicated manufacturing equipment companies, reducing the value of proprietary process development and enhancing the value of product definition and circuit design. Major semiconductor companies initially pressured these equipment vendors to “customize” each production tool to their proprietary specifications, inhibiting reduced costs of capital equipment. Japan became a major supplier of semiconductor manufacturing equipment, further exacerbating problems for the U.S. semiconductor industry. This scenario produced a strategic inflection point in the IC production: U.S. vendors of DRAM suffered financial losses and many ultimately exited the mass memory market.

This situation spawned cooperation among the major U.S. semiconductor manufacturers, resulting in the establishment of the Se...

Table of contents

• Cover
• Title
• Copyright
• Foreword to the Second Edition
• Preface to the Second Edition
• Editors
• Contributors
• Contents
• 1: Introduction to Semiconductor Devices
• 2: Overview of Interconnect—Copper and Low-K Integration
• 3: Silicon Materials
• 4: SOI Materials and Devices
• 5: Surface Preparation
• 6: Supercritical Carbon Dioxide in Semiconductor Cleaning
• 7: Ion Implantation
• 8: Dopant Diffusion
• 9: Oxidation and Gate Dielectrics
• 10: Silicides
• 11: Rapid Thermal Processing
• 12: Low-K Dielectrics
• 13: Chemical Vapor Deposition
• 14: Atomic Layer Deposition
• 15: Physical Vapor Deposition
• 16: Damascene Copper Electroplating
• 17: Chemical–Mechanical Polishing
• 18: Optical Lithography
• 19: Photoresist Materials and Processing
• 20: Photomask Fabrication
• 21: Plasma Etch
• 22: Equipment Reliability
• 23: Overview of Process Control
• 24: In-Line Metrology
• 25: In-Situ Metrology
• 26: Yield Modeling
• 27: Yield Management
• 28: Electrical, Physical, and Chemical Characterization
• 29: Failure Analysis
• 30: Reliability Physics and Engineering
• 31: Effects of Terrestrial Radiation on Integrated Circuits
• 32: Integrated-Circuit Packaging
• 33: 300 mm Wafer Fab Logistics and Automated Material Handling Systems
• 34: Factory Modeling
• 35: Economics of Semiconductor Manufacturing
• Appendix A: Physical Constants
• Appendix B: Units Conversion
• Appendix C: Standards Commonly Used in Semiconductor Manufacturing
• Appendix D: Acronyms
• Index