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Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces
High Performance Compute and System-in-Package
Beth Keser,Steffen Kröhnert
- English
- PDF
- Available on iOS & Android
Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces
High Performance Compute and System-in-Package
Beth Keser,Steffen Kröhnert
About This Book
Discover an up-to-date exploration of Embedded and Fan-Out Waver and Panel Level technologies
In Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package, a team of accomplished semiconductor experts delivers an in-depth treatment of various fan-out and embedded die approaches.
The book begins with a market analysis of the latest technology trends in Fan-Out and Wafer Level Packaging before moving on to a cost analysis of these solutions. The contributors discuss the new package types for advanced application spaces being created by companies like TSMC, Deca Technologies, and ASE Group. Finally, emerging technologies from academia are explored.
Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces is an indispensable resource for microelectronic package engineers, managers, and decision makers working with OEMs and IDMs. It is also a must-read for professors and graduate students working in microelectronics packaging research.
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Table of contents
- Cover
- Title Page
- Copyright
- Contents
- Preface
- Chapter 1 Fan-Out Wafer and Panel Level Packaging Market and Technology Trends
- Chapter 2 Cost Comparison of FO-WLP with Other Technologies
- Chapter 3 Integrated Fan-Out (InFO) for Mobile Computing
- Chapter 4 Integrated Fan-Out (InFO) for High Performance Computing
- Chapter 5 Adaptive Patterning and M-Series for High Density Integration
- Chapter 6 Panel-Level Packaging for Heterogenous Integration
- Chapter 7 Next Generation Chip Embedding Technology for High Efficiency Power Modules and Power SiPs
- Chapter 8 Die Integration Technologies on Advanced Substrates Including Embedding and Cavities
- Chapter 9 Advanced Embedded Trace Substrate - A Flexible Alternative to Fan-Out Wafer Level Packaging
- Chapter 10 Flexible Hybrid Electronics Using Fan-Out Wafer-Level Packaging
- Chapter 11 Polylithic Integrated Circuits using 2.5D and 3D Heterogeneous Integration: Electrical and Thermal Design Considerations and Demonstrations
- Index
- EULA