Multicore DSP

From Algorithms to Real-time Implementation on the TMS320C66x SoC

Naim Dahnoun

• Publisher: Wiley
• Year: 2017
• Print ISBN: 9781119003823
• eBook ISBN: 9781119003854
• Edition: 1
• Topic: Technologie et ingénierie
• Subtopic: Signaux et traitement du signal

The only book to offer special coverage of the fundamentals of multicore DSP for implementation on the TMS320C66xx SoC 

This unique book provides readers with an understanding of the TMS320C66xx SoC as well as its constraints. It offers critical analysis of each element, which not only broadens their knowledge of the subject, but aids them in gaining a better understanding of how these elements work so well together.

Written by Texas Instruments' First DSP Educator Award winner, Naim Dahnoun, the book teaches readers how to use the development tools, take advantage of the maximum performance and functionality of this processor and have an understanding of the rich content which spans from architecture, development tools and programming models, such as OpenCL and OpenMP, to debugging tools. It also covers various multicore audio and image applications in detail.  Additionally, this one-of-a-kind book is supplemented with:

• A rich set of tested laboratory exercises and solutions
• Audio and Image processing applications source code for the Code Composer Studio (integrated development environment from Texas Instruments)
• Multiple tables and illustrations

With no other book on the market offering any coverage at all on the subject and its rich content with twenty chapters, Multicore DSP: From Algorithms to Real-time Implementation on the TMS320C66x SoC is a rare and much-needed source of information for undergraduates and postgraduates in the field that allows them to make real-time applications work in a relatively short period of time. It is also incredibly beneficial to hardware and software engineers involved in programming real-time embedded systems.

1
Introduction to DSP

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CHAPTER MENU

1. 1.1 Introduction
2. 1.2 Multicore processors
   1. 1.2.1 Can any algorithm benefit from a multicore processor?
   2. 1.2.2 How many cores do I need for my application?
3. 1.3 Key applications of high‐performance multicore devices
4. 1.4 FPGAs, Multicore DSPs, GPUs and Multicore CPUs
5. 1.5 Challenges faced for programming a multicore processor
6. 1.6 Texas Instruments DSP roadmap
7. 1.7 Conclusion
8. References

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Learning how to master a system‐on‐chip (SoC) can be a long, daunting process, especially for the novice. However, keeping in mind the big picture and understanding why a specific piece of hardware or software is used will remove the complexity in the details.

The purpose of this chapter is give an overview for the need of multicore processors, list different types of multicore processors and introduce the KeyStone processors that are the subject of this book.

1.1 Introduction

Today’s microprocessors are based on switching devices that provide alternation between two states, ON and OFF, that represent 1 s and 0 s. Up to now, the transistor is the only practical device to be used. Having small, fast, low‐power transistors has always been the challenge for chip manufacturers. From the 1960s, as predicted by Gordon Moore (in Moore’s law), the number of transistors that could be fitted in an integrated circuit doubled every 24 months [1]. That was possible due to new material, the development of chip process technology and especially the advances in photolithography that pushed the transistor size from 10 µm in the 1960s to about 10 nm currently. As the transistor scaled, industry not only took advantage of the transistor count but also increased the clock speed, using various architecture enhancements such as instruction‐level parallelism (ILP) that can be achieved by superscaling (loading multiple instructions simultaneously and executing them simultaneously), pipelining (where different phases of instructions overlap), out‐of‐order execution (instructions are executed in any order, and the choice of the order is dynamic) and so on, and different power‐efficient cache levels and power‐aware software designs such as compilers for low‐power consumption [2] and low‐power instructions or instructions of variable length. However, the increase in clock frequency was not sustainable as power consumption became such a real constraint that it was not possible to produce a commercial device. In fact, chip manufacturers have abandoned the idea of continually increasing the clock frequency because it was technically challenging and costly and because power consumption was a real issue, especially for mobile computing devices such as smartphones and handheld computers and for high‐performance computers. Recently, static power consumption has also become a concern as the transistor scales, and therefore both dynamic power and static powers are to be considered. It is also worth noting at this stage that increase in the operating frequency requires power consumption increase, that is not linear with the frequency, as one can assume.

This is due to the fact that an increase in frequency will require an increase in voltage. For instance, an increase of 50% of the frequency will also result in an increase of 35% of the voltage [2].

To overcome the problem of frequency plateau, processor manufacturers like Texas Instruments (TI), ARM and Intel find that by keeping the frequency at an acceptable level and increasing the number of cores, they will be able to support many application domains that require high performance and low power. Having multicore processors is not a new idea; for instance, TI introduced a 5‐core processor in 1995 (TMS320C8x), a 2‐core processor in 1998 (TMS320C54x) and the OMAP (Open Multimedia Application Platform) family in 2002 [3], and Lucent produced a 3‐core processor in 2000. However, manufacturers and users were not that interested in multicore as the processors’ frequency increase was sufficient to satisfy the market and mul...

Table of contents

• Cover
• Title Page
• Table of Contents
• Preface
• Acknowledgements
• Foreword
• About the Companion Website
• 1 Introduction to DSP
• 2 The TMS320C66x architecture overview
• 3 Software development tools and the TMS320C6678 EVM
• 4 Numerical issues
• 5 Software optimisation
• 6 The TMS320C66x interrupts
• 7 Real‐time operating system: TI‐RTOS
• 8 Enhanced Direct Memory Access (EDMA3) controller
• 9 Inter‐Processor Communication (IPC)
• 10 Single and multicore debugging
• 11 Bootloader for KeyStone I and KeyStone II
• 12 Introduction to OpenMP
• 13 Introduction to OpenCL for the KeyStone II
• 14 Multicore Navigator
• 15 FIR filter implementation
• 16 IIR filter implementation
• 17 Adaptive filter implementation
• 18 FFT implementation
• 19 Hough transform
• 20 Stereo vision implementation
• Index
• End User License Agreement