Cascade of Adders

5 Key excerpts on "Cascade of Adders"

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  eBook - ePub

  Digital Design

  Basic Concepts and Principles

  • Mohammad A. Karim, Xinghao Chen(Authors)
  • 2017(Publication Date)
  • CRC Press

    (Publisher)

  10 . For the time being it is enough to understand that the registers in question are capable moving stored bits from left to the right.

  Sequential systems are not devoid of problems. Some of these problems often are very critical to the functioning of the system and thus must be considered very carefully. Consider the logic circuit shown in Figure 7.63 . When the input is a 0, the output becomes a 1. Since the output in turn is fed back as a input, the values of the output disagree with that of the input resulting in an indeterminate feedback system. Such problems are avoided by eliminating the conditions of continuous oscillations.

  Figure 7.62 A serial addition circuit.

  Figure 7.63 An indeterminate logic circuit.

  Figure 7.64 (a) Combinatorial circuit and (b) its corresponding timing diagram.

  To comprehend another frequently encountered problem, consider next the combinatorial logic circuit shown in Figure 7.64 a where the gates numbered 1, 2, and 3, respectively, have gate delays of Δt 1 , Δt 2 , and Δt 3 . We arbitrarily chose that at time t 0 all three inputs are 1 and at time t > t 0 the input A , for example, changes from a 1 to a 0. Figure 7.64 b shows the resulting timing diagram provided that Δt 1 < Δt 2 . It is apparent that the combinatorial circuit output results in a transient error pulse for a period given by Δt 2 – Δt 1 . This type of an output is a consequence of the hazard problem discussed earlier in Chapter 2

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  eBook - ePub

  Intelligent Circuits and Systems

  • Rajesh Singh, Anita Gehlot, Rajesh Singh, Anita Gehlot(Authors)
  • 2021(Publication Date)
  • CRC Press

    (Publisher)

  8 ] have looked at various adders namely parallel prefix adders (PPA), MCC etc.

  We have implemented, compared and evaluated four types of adders based on delay, area, power dissipation and leakage current. The adders implemented and simulated were 4-bit RCA, CLA, MCC and CSK. Cadence Virtuoso has been used for implementation of the adder circuits and ELDO was used for simulation and analysis. All the work has been carried out on 28nm technology within the supply voltage range of 0.6–1.0 V.

  2. Designs

  For a particular combination of inputs Aj and Bj, the propagate signal Pj determines whether the carry-in to the jth block would propagate to the output, whereas the generate signal Gj determines if a carry-out would be set from inside the block independently from the inputs. The expression for Gj and Pj with two input binary operands, Aj and Bj as given by [9 ,10 ] can be expressed as follows:

  Gj = Aj • Bj

  (I)

  Pj = Aj ⨁ Bj

  (II)

  The sum and carry Boolean expression for ith stage of an adder are:

  Sj = Pj ⨁ Cj

  (III)

  C

  j+1

  = Gj + Pj • Cj

  (IV)

  The signals are created as per (I), for each bit position in CLA. Further the sum and carry are given by eq. (III) and (IV).

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  eBook - ePub

  Introduction to Digital Electronics

  • J. Crowe, Barrie Hayes-Gill(Authors)
  • 1998(Publication Date)
  • Butterworth-Heinemann

    (Publisher)

  This rippling limits the operational speed of the circuit which is dependent upon the number of gates the carry signal has to pass through. Since each full adder is a two-level circuit, the full four-bit ripple carry adder is an eight-level implementation. So after applying the inputs to the adder, the correct output cannot be guaranteed to appear until a time equal to eight propagation delays of the gates being used has elapsed.

  The advantage of the circuit is that as each full adder is composed of five gates4 then only 20 gates are needed. The ripple carry, or parallel adder, is therefore a practical solution to the production of a four-bit adder. This circuit is an example of an iterative or systolic array, which is the name given to a combinational circuit that uses relatively simple blocks (the full adders) connected together to perform a more complex function.

  Look-ahead carry adder

  The fourth possible implementation of a four-bit binary adder bears some resemblance to the ripple carry adder, but overcomes the problem of the ‘rippling’ carry by using extra circuitry to predict this rippling in advance. This gives a speed advantage at the expense of a more complex circuit, which is a demonstration of a general rule that any gain in performance in some aspect of a circuit is usually matched by a loss in performance of another.

  Reconsidering the ripple carry adder and denoting the carry-out from each stage by Cn , where n is the stage number, and the initial carry-in bit as

  Ci

  , we begin with the first stage and derive the Boolean expression for C 0 . (We know what it is from the Karnaugh map in Section 4.1.5 ). So:

  Similarly for the second stage:

  This expression demonstrates the problem of the ripple carry adder, because C 1 depends upon C 0 which must be produced first. However, we already have an expression for C 0 in terms of the actual inputs to the adder, so we can substitute this into C 1 so removing the rippling problem. This gives:

  This is a rather unwieldy expression, but we can simplify it by letting, for a general stage, j :

  This gives Continuing this process also gives:

  This gives all four carry-outs in terms of the inputs, which means they can be produced as soon as the inputs are applied to the circuit

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  eBook - ePub

  VLSI Design

  • M. Michael Vai(Author)
  • 2017(Publication Date)
  • CRC Press

    (Publisher)

  Fig. 7.2 Ripple carry adder.

  Fig. 7.3 Full adder tessellation.

  A ripple-carry adder has a computation time that is proportional to the number of bits in its operands. The wider the operands, the longer does it take the ripple-carry adder to complete its addition. Whether this presents a limitation or not on the use of a ripple-carry adder naturally depends on the application on hand. A designer must be able to balance the benefits and limitations of a specific structure so that an intelligent building block selection can be made.

  General expressions can be developed for the purpose of building block evaluation and comparison. For example, the area (A rca ), computation time (D rca ), and power consumption (P rca ) of an n -bit ripple-carry adder can be estimated as

  A

  r c a

  = n

  A

  F a

  ⁢

  ( 7.1 )

  Δ

  r c a

  = n

  Δ

  F A

  ⁢

  ( 7.2 )

  P

  r c a

  = n

  P

  F A

  ⁢

  ( 7.3 )

  where A FA , P FA , and D FA are the area, computation time, and power consumption of the one-bit full adder being used, respectively.

  Carry Select Adder

  The addition time of a ripple-carry adder can be improved with a modified structure called the carry select adder. It retains the layout regularity of a ripple-carry adder. The principle of a carry select adder is to use one ripple-carry adder to execute an addition assuming that the carry-in is 1. Another ripple-carry adder is used to execute the same addition assuming that the carry-in is 0. The real carry-in computed in a previous stage is used to select one of the two sums with a multiplexer. Fig. 7.4 shows an example of an 8-bit carry select adder with a 4-4 staging. The 4-4 staging specifies that two stages are to be used, each of which performs the addition of 4 bits.

  Fig. 7.4 8-bit carry select adder.

  All three 4-bit ripple-carry adders in the carry select adder work in parallel. The addition time is thus the delay of the first stage 4-bit ripple-carry adder plus the delay of a multiplexer. For longer operands, the use of stages with identical lengths does not necessarily lead to an optimal delay. This is caused by the different delays of the selecting carry bits which have to go through different levels of multiplexers. A circuit level analysis can be performed to determine the best staging scheme for a given technology (see Problem 7.1).

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  eBook - ePub

  Digital Logic Design

  • Brian Holdsworth, Clive Woods(Authors)
  • 2002(Publication Date)
  • Newnes

    (Publisher)

  n.

  The four full adders shown in Figure 12.4 can all be implemented on a single 16-pin chip to provide a 4-bit MSI adder. Eight inputs are required for the operands, four for the sum outputs, one each for the carry-in and carry-out, and two pins for the supply voltage. A typical example of a 4-bit adder in the TTL family is the 74283 and the new functional logic symbol for this chip is shown in Figure A.24 (see appendix).

  12.6 Carry look-ahead addition

  The performance of the 4-bit parallel adder described in the previous section can be improved by increasing the speed of operation. This can be achieved by using gates having a reduced propagation delay or by designing a circuit that minimises the delay generated by the carry circuit. In practice such a circuit requires more hardware and the improvement gained is a trade-off between cost and increased speed. Several methods have been developed for reducing the addition time and one of these, the carry look-ahead technique, will be described here.

  The carry-output equation for a full adder may be written: or as:

  where

  P = A B

  is referred to as the propagation term, and G = AB is called the generation term. If G = 1, then A = B = 1, and a carry is generated in the stage defined by the C out equation. Additionally, if the carry into the stage C in = 1, and either A or B is 1, then the input carry will be propagated to the next stage. For a 4-bit adder the generation and propagation terms for each stage are:

  while the carries for the various stages are:

  Substituting for C 0 in the C 1 equation and similarly in successive equations, leads to the following equation for the carry out C 3 from the most significant stage of a 4-bit adder:

  This carry-out equation can be implemented by the 2-level AND/OR circuit, shown in Figure 12.5

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