Full Adder

11 Key excerpts on "Full Adder"

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  eBook - ePub

  Digital Electronics 2

  Sequential and Arithmetic Logic Circuits

  • Tertulien Ndjountche(Author)
  • 2016(Publication Date)
  • Wiley-ISTE

    (Publisher)

  4 Arithmetic and Logic Circuits

  4.1. Introduction

  Arithmetic circuits are essential in the implementation of microprocessors and circuits for digital signal processing.

  As the complexity of the direct approach (construct a truth table and then derive and simplify the output logic equations) increases with an increase in the size of data, the modular approach is often chosen to implement arithmetic circuits. A given digital circuit is thus implemented by assembling modules that are designed for numbers with small word lengths.

  Despite the increasing number of arithmetic operations that are becoming routine, most microprocessors only contain circuits for basic operations, such as an adder (or summer), comparator, multiplier and divider. In addition to arithmetic circuits, there is also a need for circuits that can perform bitwise logic and shift operations. One of the main components of a microprocessor, therefore, is the arithmetic and logic unit (ALU), which encases all the circuits required for carrying out operations on digital data.

  4.2. Adder

  Adders are used to perform a large number of digital operations. In spite of the apparent simplicity of an addition operation, there are several approaches to designing adders.

  4.2.1. Half adder

  A half adder (HA) is a circuit that generates the sum, S, and the carry, C, resulting from the addition of two 1-bit numbers, A and B.

  An example of a simple addition, A + B, is given in Figure 4.1 . The truth table shown in Table 4.1 is constructed by considering bits C and S to be the MSB and LSB in the 2-bit representation of the addition result. The logic equations for the two outputs are given by:

  [4.1]

  [4.2]

  Figure 4.1. Example of a simple addition. For a color version of the figure, see www.iste.co.uk/ndjountche/electronics2.zip

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  eBook - ePub

  VLSI Design

  • M. Michael Vai(Author)
  • 2017(Publication Date)
  • CRC Press

    (Publisher)

  i ). An alternative view of the one-bit Full Adder is that it accepts three 1-bit operands and produces a two-bit sum.

  Fig. 7.1 One-bit full-adder.

  A number of one-bit Full Adders can be cascaded to form a ripple-carry adder (see Fig. 7.2 ). The ripple-carry adder is extremely modular since it contains only one-bit Full Adders. The structure is also very regular. All Full Adders in the ripple-carry adder are connected to their neighbors in the same way. The interconnections within the ripple-carry adder are limited to between neighboring Full Adders.

  The Full Adder cell can be laid out to accept a carry-in bit (c

  i −1

  ) from its right edge and produces a carry-out bit (c i ) at its left edge. This layout will facilitate the use of tessellation to the design of a ripple-carry adder. Fig. 7.3 illustrates that when two Full Adder cells are placed side by side, their power rails (V DD and V SS ) as well as their carry paths are connected. It is also quite simple to expand a ripple-carry adder. An n -bit ripple-carry adder can be expanded to accept (n + m )-bit operands by incorporating m additional full-adder cells.

  Fig. 7.2 Ripple carry adder.

  Fig. 7.3 Full Adder tessellation.

  A ripple-carry adder has a computation time that is proportional to the number of bits in its operands. The wider the operands, the longer does it take the ripple-carry adder to complete its addition. Whether this presents a limitation or not on the use of a ripple-carry adder naturally depends on the application on hand. A designer must be able to balance the benefits and limitations of a specific structure so that an intelligent building block selection can be made.

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  Digital Design and Verilog HDL Fundamentals

  • Joseph Cavanagh(Author)
  • 2017(Publication Date)
  • CRC Press

    (Publisher)

  Figure 6.2 .

  Table 6.1 Truth Table for a Full Adder

  s u m = a ' b '   c i n + a ' b   c i n ' + a b '   c i n ' + a b   c i n

  ⁢ ( 6.1 )

  c o u t = a ' b   c i n + a b '   c i n + a b   c i n ' + a b   c i n

  ⁢ ( 6.2 )

  Figure 6.1 Karnaugh map for the carry-out of a Full Adder.

  c o u

  t i

  = a b + a c i n + b c i n

  ⁢ ( 6.3 )

  Figure 6.2 Logic diagram for a high-speed Full Adder.

  The design module is shown in Figure 6.3 , which correlates the instantiation names and the net names with the logic diagram. The following NAND gates are instantiated into the structural module: nand2_df, nand3_df, and nand4_df. These NAND gates have been previously designed. The test bench module is shown in Figure 6.4 . The outputs and waveforms are shown in Figure 6.5 and Figure 6.6 , respectively.

  Figure 6.3 Design module for the high-speed Full Adder.

  Figure 6.4 Test bench for the high-speed Full Adder.

  Figure 6.5 Outputs for the high-speed Full Adder.

  Figure 6.6 Waveforms for the high-speed Full Adder.

  6.1.2 Four-Bit Ripple Adder

  A ripple adder is a relatively low-speed adder because there is no carry-lookahead feature. A 4-bit ripple adder consists of four Full Adders connected serially in which the carry-out of stagei is carry-in to stagei +1

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  Fundamentals of Digital Logic and Microcontrollers

  • M. Rafiquzzaman(Author)
  • 2014(Publication Date)
  • Wiley

    (Publisher)

  Figure 4.26 Logic diagram of the half-adder.

  Step 1: Truth Table: Table 4.13 shows the truth table of the half-adder.

  Table 4.13

  Truth Table of the Half-Adder

  Step 2: Minimization: Output equations cannot be minimized using K-maps. Hence, output equations are obtained directly from the truth table as follows:

  Step 3: Schematic: Figure 4.27 shows the logic diagram of the half-adder.

  Figure 4.27

  Block diagram of a Full Adder.

  Next, consider addition of two 4-bit numbers as follows:

  This addition of two bits will generate a sum bit and a carry bit. The carry may be 0 or 1. Also, there will be no previous carry while adding the least significant bits (bit 0) of the two numbers. This means that two bits need to be added for bit 0 of the two numbers. On the other hand, addition of three bits (two bits of the two numbers and a previous carry, which may be 0 or 1) is required for all the subsequent bits. Hence, an adder is needed to add three bits. A combinational circuit that adds three bits, generating a sum bit and a carry bit (which may be 0 or 1), is called a Full Adder. Figure 4.28 shows the block diagram of a Full Adder. The Full Adder adds three bits, x, y, and z, and generates a sum bit (S) and a carry bit (C). The Full Adder is designed next. Three design steps are provided below.

  Figure 4.28

  K-map for C and the schematic of the Full Adder.

  Step 1: Truth Table: Table 4.14 shows the truth table of the Full Adder.

  Table 4.14

  Truth Table of the Full Adder

  Step 2: Minimization: The sum, S cannot be minimized using a K-map. Hence, the equation for the sum, S

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  Numbers

  Arithmetic and Computation

  • Asok Kumar Mallik, Amit Kumar Das(Authors)
  • 2022(Publication Date)
  • CRC Press

    (Publisher)

  We may discuss next how a computer using numbers in binary form can carry out the basic arithmetic operations; at least addition. Dropping all other issues we focus on the core part of the computer that carries out addition.

  6.2 A computer as a black box

  Confronted with the challenge of building at least the core arithmetic part of the computer let us make a modest beginning. Consider a computer as a black box (see Fig. 6.3) . It receives binary input and produces binary outputs and could carry out addition only. Now we may focus on how addition is carried out, to figure out the logic circuits that will be present inside the black box.

  Fig. 6.3: Computer as a black box

  How do we add?

  The numbers will be represented in binary; i.e. finite number of bits together in the form of a bit-string. Thus, an n-bit number, say A, in binary would be represented as An− 1 An− 2 …A1 A0. To make the matter simple consider the problem of adding two bits at a time. Here we have only four input combinations in binary instead of 100 different combinations needed for the decimal.

  The addition logic in a tabular form, the Half-adder (HA) truth-table to be precise, is presented in Fig. 6.4.

  Fig. 6.4: Truth-table for a half-adder.

  Here, A and B represent the bits to be added (and not the n-bit string) while the carry (C) and the sum (S) together represent the outcome. Note that considering the inputs as binary digits (i.e. 0 and 1) we see that the truth-table complies with the addition of two 1-bit binary numbers.

  Before we construct a half-adder or other logic circuits introduction to logic operations and logic gates is required and is discussed next.

  6.3 Logic operation and logic gates

  Logic circuits based on logic operations are the basic building blocks in a computer. The three primitive logic operations are (i) NOT, (ii) AND, and (iii) OR, the corresponding implementations, usually using electronic circuitry are known as logic gates. We are not actually bothered with the exact implementation of the logic circuitry and use only the logic gate symbols to avoid complexity.

  6.3.1 NOT, AND and OR logic

  Fig. 6.5

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  Verilog HDL Design Examples

  • Joseph Cavanagh(Author)
  • 2017(Publication Date)
  • CRC Press

    (Publisher)

  2 .

  Table 4.1 Truth Table for a Full Adder for Binary Addition

  The radix complement of binary numbers (2s complement ) is obtained by complementing each bit of the corresponding positive binary number and adding 1 to the low–order bit position. For example, let A = 0001 11002 = +2810 and A’ = 1110 0011 = 1110 0100 = –28. To obtain the value of a negative number count the weight of the 0s and add 1. Examples of addition operations are shown in Table 4.2 , which add two 8-bit positive and negative operands.

  Table 4.2 Examples of Addition for Two Eight-Bit Signed Operands

  4.12.1 Full Adder

  A Full Adder can be designed from two half adders. A half adder adds two operand bits a and b, and produces two outputs sum and carry-out . The truth table for a half adder is shown in Table 4.3 and the equations for a half adder are shown in Equation 4.2 . From Table 4.1 , the equations for the sum and carry-out of a Full Adder are shown in Equation 4.3 . The logic diagram for a Full Adder is shown in Figure 4.1 .

  (4.2)

  s u m =

  a ′

  b + a b = a ⊕ b c o u t = a b

  (4.3)

  c o u n t =

  a ′

  b c i n + a

  b ′

  c i n + a b c i

  n ′

  + a b c i n

  = a b + ( a ⊕ b ) c i n

  Table 4.3 Truth Table for a Half Adder

  Augend (a )	Addend (b )	Carry-out (cout )	Sum
  0	0	0	0
  0	1	0	1
  1	0	0	1
  1	1	1	0

  Figure 4.1 Logic diagram for a Full Adder using two half adders.

  The structural design module is shown in Figure 4.2 using built-in primitives. The test bench module and the outputs are shown in Figures 4.3 and 4.4

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  Digital Logic Techniques

  • John Stonham(Author)
  • 2017(Publication Date)
  • CRC Press

    (Publisher)

  Design of arithmetic processors 7

  Objectives

  □ To design logic circuits for arithmetic. □ To examine ways of increasing the speed of arithmetic units. □ To develop a programmable arithmetic unit capable of performing a number of arithmetic calculations. □ To introduce the concept of a programming language.

  An important application of logic is in an arithmetic unit. Such a device must be capable of being reconfigured to enable it to carry out a range of numerical operations. This ability to carry out many different operations, depending on the problem needing to be solved, leads to the concept of a programmable system – a computer. The main components of an arithmetic unit will be developed in this chapter and a simple system controller will be specified. An elementary programming language for operating this system will be developed.

  Ripple-through-carry addition

  The addition of two binary inputs has already been considered in Chapter 3 . The combinational logic designs for a Full Adder circuit which accepts input bits A and B and generates the sum A plus B, plus any carry-in together with the resulting carry-out, are given in Fig. 3.9 . This Full Adder circuit can only provide the sum of two single-bit inputs – a very limited device. To extend the resolution of the adder, the cells can be cascaded where each cell receives one corresponding bit from each of the two input numbers to be added together and the carry is propagated from cell to cell as shown in Fig. 7.1 .

  See page 59. Any system must be designed for the worst case – it could happen in practice.

  Such a system is known as a ripple-through-carry adder because in the worst case each cell produces a carry and each successive cell cannot generate the correct summation until the previous, i.e. lesser significant cell, has generated its carry output. Consider a ripple-through-carry adder of 8-bits resolution, performing the addition A + B where

  A = 12710 and B = 110

  Fig. 7.1

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  Introduction to Logic Design

  • Sajjan G. Shiva(Author)
  • 2018(Publication Date)
  • CRC Press

    (Publisher)

  Addition is the most common arithmetic operation performed by a digital computer. If the computer hardware can add two binary numbers, the other three primitive arithmetic operations can be performed with the additional hardware: subtraction is performed by adding the negative of the subtrahend expressed in either twos or ones complement form to the minuend; multiplication involves the repeated addition of the multiplicand to itself; and division involves the repeated subtraction of the divisor from the dividend. Because of the cost of hardware, earlier computers implemented addition in the hardware and used this hardware to realize the other three arithmetic operations by software means (i.e., programming the addition hardware). It is now cost-effective to use hardware to realize all the arithmetic operations. In this section, we will examine some popular adder circuits.

  5.2.1    Parallel Binary Adder (PBA)

  Consider the addition of two four-bit numbers (A and B):

  Here, a0 and b0 are the least significant bits (LSBs), and a3 and b3 are the most significant bits (MSBs). The addition is performed starting with the LSB position. Addition of a0 and b0 yields the sum bit s0 and a carry of c0 . The carry c0 is then used in the addition of the bits in the next most significant stage. That is, c0 , a1 and b1 are added, yielding s1 and c1 . This addition process is repeated through the MSB position and applies to the addition of numbers with any number of bits.

  A Parallel Binary Adder (BPA) implements this addition process by using two types of adder circuits: a half-adder and a Full Adder. In particular, for adding two n-bit numbers, the PBA uses one half-adder at the LSB stage and n – 1 Full Adders. The addition of bits is done in parallel since n adders are available, one for each bit position.

  Figure 5.1 shows the PBA circuit for the four-bit addition. A half-adder is a device that can add two bits producing a SUM and a CARRY as outputs. A Full Adder adds three input bits and produces a SUM output and a CARRY-OUT output. One of the inputs to the Full Adder is called CARRY-IN. (Each of these devices is a two-level circuit, as will be shown later in this section.)

  Figure 5.1 A ripple-carry adder.

  In the PBA circuit of Figure 5.1

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  Computer Principles and Design in Verilog HDL

  • Yamin Li(Author)
  • 2015(Publication Date)
  • Wiley

    (Publisher)

  You can see that the same binary bit pattern can have different meanings. Table 3.2 The values of 4-bit binary numbers at different representations Binary number Unsigned 2's complement Sign-absolute Biased 3.2 Binary Addition and Subtraction This section describes the binary addition and subtraction algorithms and their implementations in Verilog HDL. A carry-lookahead adder (CLA) is also described. 3.2.1 Ripple Adder and Subtracter Design The circuit that adds two 1-bit numbers is called a half adder. The half adder performs,,, and. The left bit of the result is called a carry out and the right bit is called a sum. A Full Adder adds not only the two 1-bit numbers but also a carry in which is the carry out of the next bit to the right. Let's see the 4-bit addition example shown in Figure 3.3. The three inputs of a Full Adder are a, b, and ci (carry in), and the outputs are co (carry out) and s (sum). Figure 3.3 Addition of two 4-bit numbers Table 3.3 Truth table of a Full Adder Input signal Output signal Comment a b ci co s 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 Table 3.3 is the truth table for designing the circuit of the Full Adder. From the truth table or Karnaugh maps, we can get the following expressions: Then we can design the circuit of the Full Adder, as shown in Figure 3.4. Figure 3.4 Schematic diagram of the Full Adder Because, we can also have the Full Adder circuit as shown in Figure 3.5. Figure 3.5 Schematic diagram of Full Adder (using XOR gates) The following is the structural style Verilog HDL code of the Full Adder

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  Algorithms and Data Structures in C++

  • Alan Parker(Author)
  • 2018(Publication Date)
  • Routledge

    (Publisher)

  Code List 4.1

  C++ Output

  a=−6 b=6 sum = 0 overflow= 0 carry= 1 a= 19 b= −33 sum = −14 overflow= 0 carry= 0 a= −60 b= −90 sum = 106 overflow= 1 carry= 1 a= −1 b= −2 sum = −3 overflow= 0 carry= 1 a= −128 b= −128 sum = 0 overflow= 1 carry= 1

  The programs do not check for overflow but simply simulate the additon as performed by hardware. 4.1.1    Full and Half Adder

  In order to develop some fast algorithms for multiplication and addition it is necessary to analyze the process of addition and multiplication at the bit level. Full and half adders are bit-level building blocks that are used to perform addition.

  A half adder is a module which inputs two signals, a

  i

  and b

  i

  , and generates a sum, s

  i

  , and a carry-out c

  i

  . A half adder does not support a carry-in. The outputs are as in Table 4.1 .

  TABLE 4.1 Half Adder Truth Table

  A Full Adder has a carry-in input, c

  i

  A Full Adder is shown in Table 4.2 .

  TABLE 4.2 Full Adder Truth Table

  The Full Adder and half adder modules are shown in Figure 4.1 . The boolean equation for the output of the Full Adder is

  s i = a ¯ i b ¯ i c i − 1 + a ¯ i b i c i − 1 ¯ + a i b ¯ i c i − 1 ¯ + a i b i c i − 1

  (4.1)

  c i = a ¯ i b i c i − 1 + a i b i c i − 1 ¯ + a i b i c i − 1

  (4.2)

  The boolean equation for the output of the half adder is

  s i = a i b ¯ i + a ¯ i b i = a i ⊕ b i

  (4.3)

  where ⊕ denotes the exclusive-or operation.

  c i = a i b i

  (4.4)

  The output delay of each module can be expressed in terms of the gate delay, Δ, of the technology used to implement the boolean expression. The sum, s

  i

  , for the Full Adder can be implemented as in Eq. 4.1 using four 3-input NAND gates in parallel followed by a 4-input NAND gate. The gate delay of a k-input NAND gate is Δ so the sum is calculated in 2Δ. This is illustrated in Figure 4.2 . For the half-adder the sum is calculated within 1Δ and the carry is generated within 1Δ. The Output Delay for the Half Adder is shown in Figure 4.2

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  Digital Design

  Basic Concepts and Principles

  • Mohammad Karim, Xinghao Chen(Authors)
  • 2017(Publication Date)
  • CRC Press

    (Publisher)

  Synchronous Arithmetic 10.1 Introduction A number of important combinatorial as well as sequential subsystems design such as those of multibit adders, registers, counters, decoders, multiplexers, and comparators have already been explored. We have also introduced register transfer language (RTL) and shown how it can be used to assemble various combinatorial and sequential modules to form more complex digital systems. One of our goals is to comprehend sufficiently how complex digital systems work in order to be able to design and assemble functional components. Digital computers, in particular, often involve multiple transfers of multibit data between registers and at appropriate times subject these data sets to multibit arithmetic and or logic operations. The register transfers are often interlinked with the control unit that coordinates data transfers as well as executes arithmetic and /or logic operations in a specific order. The RTL algorithm that describes the sequence of operations provides enough clues for the design of data as well as the corresponding control unit. This chapter introduces the RTL algorithms necessary for implementing primarily sequential arithmetic operations. 10.2 Serial Adder/Subtractor We introduced earlier the concept of binary serial addition and in connection to that operation had discussed a sequential logic circuit as shown in. In serial addition, we start with the LSB; one bit of addend and one bit of augend are shifted right into a single-bit FA. The resultant sum bit is stored then at the MSB of either the addend or augend register. Coincident with the clock, the carry-out of the current add operation is fed back as carry-in to the same FA; the other two FA inputs will include the next pair of shifted addend and augend bits. This shift and add operations cycle is repeated until all bits of the addend and augend have been processed

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