Computer Science
Memory Data Register
A Memory Data Register (MDR) is a register in a computer's central processing unit (CPU) that stores the data being transferred to or from the main memory. It acts as a buffer between the CPU and the memory, allowing the CPU to access data quickly and efficiently. The MDR is also known as the Memory Buffer Register (MBR).
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3 Key excerpts on "Memory Data Register"
- eBook - ePub
Computer Architecture and Security
Fundamentals of Designing Secure Computer Systems
- Shuangbao Paul Wang, Robert S. Ledley(Authors)
- 2012(Publication Date)
- Wiley(Publisher)
Registers are used in many different ways in a computer. One can be used to hold the address of current instruction being executed. It is called program counter register (PC). The instruction register (IR) holds the actual instruction being executed currently by the computer. The status register holds several 1-bit registers and each one keeps track of special conditions of the CPU. The flags contain information such as arithmetic carry, negative sign, overflow and other critical information that is monitored by the control unit.Memory, or random access memory (RAM) can be individually accessed in a random manner. A computer memory system usually contains billions of single 1-bit memory units. In order to access those memory units, a processor uses two registers: memory address register (MAR) and Memory Data Register (MDR) (Foster and Iberall, 1985). Sometimes a Memory Data Register is referred to as a memory buffer register as it holds the data that is being stored or retrieved from the memory location currently addressed by the memory address register.Figure 3.5 shows the relationship between the MAR, MDR and memory. An address decoder is used to reduce the number of addresses required for the large number of memory units. For example, a 32-bit address bus can address 232 = 4G memory.Figure 3.5 The relationship between the MAR, MDR, and memoryIn MAR, the highest bit called most significant bit (MSB) and the lowest bit called the least significant bit (LSB) (Randell, 1982). In MDR, the number of bits that can be accessed at the same time is determined by the width of the register that is connected to the processor. For a 32-bit data bus, one instruction can process 32-bit data. While 64-bit data can be processed within one instruction for a 64-bit data bus. So generally speaking a 64-bit computer is faster. - eBook - ePub
Computer Fundamentals - 8th Edition
Concepts, Systems & Applications
- Pradeep K.Sinha(Author)
- 2004(Publication Date)
- BPB Publications(Publisher)
Memory Address Register (MAR). It holds the address of the active memory location. It is loaded from program control register when the system reads an instruction from memory.- Memory Buffer Register (MBR). It holds the contents of the accessed (read/written) memory word. The system transfers an instruction word placed in this register to instruction register. A data word placed in this register is accessible for operation with accumulator register or for transfer to I/O register. To store a word in a memory location, the system first transfers it to MBR and then writes it in memory from MBR.
- Program Control register (PC). It holds the address of the next instruction for execution. Normally, a system stores instructions of a program in consecutive memory locations, and executes them in sequence unless it encounters a branch instruction. A branch instruction is an operation that causes a transfer to a non-consecutive instruction. The system transfers address part of a branch instruction to PC register so that it becomes the address of the next instruction.
- Accumulator register (A). It holds the data on which the system has to operate, intermediate results, and results of operations performed. The system uses it during execution of most instructions. The system returns the result of an arithmetic operation to accumulator register for transfer to main memory through memory buffer register. In many computers, there are more than one accumulator registers.
- Instruction register (I). It holds the current instruction under execution. As soon as the instruction is stored in this register, its operation and address parts (see Chapter 12 ) are separated. The system sends the address part of the instruction to MAR, while it sends operation part to control unit, where it is decoded and interpreted. Finally, the control unit generates and sends command signals to the appropriate unit for carrying out the task specified in the instruction.
- Input/Output register (I/O).
- eBook - ePub
Programming for Problem-solving with C
Formulating algorithms for complex problems (English Edition)
- Dr. Kamaldeep(Author)
- 2023(Publication Date)
- BPB Publications(Publisher)
The upcoming chapter will discuss computer software and its classification on various parameters. It will also give a basic introduction to the operating system and its classifications on different parameters such as the execution of the program, number of users, and interface. Additionally, we will explore the concept of malicious programs.Points to remember- The CPU processes input device data. It is the computer’s brain.
- The ALU performs arithmetic and logic operations.
- The CU acts as the computer’s central nervous system, generating control signals to manage and control all components.
- Registers are fast, accessible memory within the CPU, holding a small amount of data measured by the number of bits it can store.
- The PC register stores the next instruction’s address.
- The MAR holds the address of data or instructions that need to be accessed from or written to the main memory.
- The MDR works as a buffer between memory and CPU.
- The accumulator interacts with ALU and stores its input/output results.
- The current instruction being executed is stored in the IR.
- Machine cycle = Fetch cycle + Execute cycle.
- The clock speed refers to the CPU’s instruction execution rate, measured in Hz (hertz). A dual-core processor contains two cores (processing elements).
- A cache is fast and located between the CPU and the main memory. L1 is placed on the CPU. The L2 and L3 are placed outside the CPU.
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