Program Counter

5 Key excerpts on "Program Counter"

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  eBook - ePub

  Embedded Systems and Computer Architecture

  • Graham R Wilson(Author)
  • 2001(Publication Date)
  • Newnes

    (Publisher)

  7 . Because we will want to transfer data from memory to registers A and T, a data path from the memory Data connections to these registers is provided. This path is along the Data Bus. Since we shall also need to store the contents of register A in memory, we make the data path between the memory and register A bi-directional.

  5.4.2 Program Counter

  An obvious way of storing program instructions is to store them in sequential locations in the memory, so we provide a 16-bit counter circuit to hold the address of the storage location from where the next instruction is to be read. This counter is called the Program Counter, PC, or Instruction Pointer, IP, since it points to the memory location that holds the next instruction. We will arrange for the Program Counter to be automatically incremented each time an instruction is read. The PC is connected to the address pins of the memory via the address bus.

  5.4.3 Operation of Simple Machine

  The machine is designed to operate by repeating the following two phases for every instruction in the program.

  Phase 1 – Instruction fetch

  The Control Unit generates the control signals that copy an instruction byte from the memory into the Instruction Register, IR. The address of this instruction is in the Program Counter, PC.

  Phase 2 – Instruction execute

  The 8 bits in the IR are connected to the Control Unit. These 8 bits determine the sequence of control signals that the Control Unit generates. The sequence of control signals generated by the Control Unit causes the execution of the instruction. The sequence finishes by starting Phase 1, so fetching the next instruction into the IR.

  The Control Unit is a complex sequential circuit having inputs from the IR that determine the sequence of control signals that the Control Unit generates. The system clock signal determines the timing of all these control signals. There are a large number of control signals. Thus there will be a control signal that is connected to the enable input of a three-state buffer that connects a register to a bus. There will be other signals that are connected to the load input of every register so causing that register to be loaded from the bus. Yet other signals will go to the ALU_mode control signals of the ALU causing the ALU to be set to perform a particular arithmetic or logical operation. Another control signal is connected to the WriteEnable input of the memory so determining whether the memory will read or write.

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  eBook - ePub

  Electronics Simplified

  • Ian Sinclair(Author)
  • 2011(Publication Date)
  • Newnes

    (Publisher)

  The exception is in the case of a jump, caused by an interrupt (see later) or by a software instruction. A jump in this sense means that a new address will be placed into the Program Counter register, and the microprocessor will then read a new instruction starting at this address and incrementing the address number at the end of each instruction. For the moment, however, the important point is that the normal action is one of incrementing the memory address each time a program action has been executed, and the sequence of actions is all important. Note Many microprocessors are designed so that they will automatically read a byte from some fixed address when they start operating. This byte is always a jump instruction, followed by data, that will cause another address range to be used. This allows the programmer to specify where the main program will be located. Note The Program Counter (PC) or instruction pointer (IP) register is the main addressing register, and is connected by gates to the address pins of the microprocessor. The number in this register will be initialized by a voltage applied to a RESET pin, and it is automatically incremented each time an instruction has been executed, or when an instruction calls for another byte. Imagine, for example, that the whole of the RAM memory from address 0000 is filled with an NOP instruction byte. NOP means no operation, and its action is simply to do nothing, just go on to the next instruction. If the PC is reset to contain the address 0000, then the NOP byte (which might be 00) at this address will be read, decoded, and acted on

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  eBook - ePub

  Computer Systems Architecture

  • Aharon Yadin(Author)
  • 2016(Publication Date)
  • Chapman and Hall/CRC

    (Publisher)

  Due to their speed, registers are considered as the top of the memory hierarchy (this term will be explained and elaborated in the next two chapters). Originally, the registers were developed in order to support the hardware operations; today’s modern processors are using many registers as part of their normal operations. For example, every system should have an internal register (sometimes called Program Counter [PC]) that holds the address of the next instruction to be executed. When the CU has to fetch the next instruction for execution, it checks the PC to determine the address of that instruction. The PC can be seen as the queue number display often used by various service organizations. This register is maintained by the hardware and the software (applications or operating system) cannot modify it, although its content is changing according to the software behavior. For example, every loop in any application has a conditional branch * and holds the potential to indirectly change the content of the PC register. Furthermore, when executing the instructions, the ALU accesses only internal registers. This means that the CU that fetches the instruction’s operands actually places the operands in these internal registers. After the ALU has finished the execution, the result is placed in another internal register and once again, the CU is responsible for copying its content to the required destination (as defined in the instruction). For example, assuming the instruction to be executed is: C = A + B Regardless of the specific programming language, during compilation the instruction will be translated into a binary mnemonic that represents the ADD instruction. In this case A, B, and C are three variables and the intent of the instruction is to replace the content of variable C by the sum of A and B

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  eBook - ePub

  Computer Architecture

  Fundamentals and Principles of Computer Design, Second Edition

  • Joseph D. Dumas II(Author)
  • 2016(Publication Date)
  • CRC Press

    (Publisher)

  based indexed addressing mode built into the Intel x86 architecture.) Such a mode, if provided, complicates the design of the processor somewhat but provides a way for the assembly language programmer (or compiler) to easily access elements of two-dimensional arrays or matrices stored in memory.

  Figure 3.9 Indexed addressing.

  Program Counter relative addressing is used in many computer architectures for handling control transfers, such as conditional branches and subroutine calls. The idea is that an offset (usually signed to allow forward or backward branching) is added to the current Program Counter (PC) value to form the destination address. This value is copied back to the PC, effectively transferring control to that address (see Figure 3.10 ).

  The advantage of using PC relative addressing, rather than simply specifying an absolute address as the destination, is that the resulting code is position independent—that is, it can be loaded anywhere in memory and still execute properly. The absolute address of a called routine or branch target may have changed, but it is still in the same place relative to the instruction that transfers control to it. For this reason, most computer architectures provide at least some subset of control transfer instructions that operate this way. Some architectures (the Motorola 680x0 family is a notable example) also implement PC relative addressing for instructions that access memory for operands. In this way, blocks of data can be relocated along with code in memory and still appear to the program logic to be in the same place.

  Figure 3.10 PC relative addressing.

  Stack addressing

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  eBook - ePub

  Computer Architecture

  Software Aspects, Coding, and Hardware

  • John Y. Hsu(Author)
  • 2017(Publication Date)
  • CRC Press

    (Publisher)

  The IAR points to the next instruction in memory. In a simple model, after retrieving an instruction in the IR, the IU increments the IAR by the length of instruction. In first generation computers, each machine instruction is one word long, so the IAR is a counter that contains a word address. If the instruction length is fixed, the IAR becomes a Program Counter.

  3.3.2.1 IAR vs. Program-Counter

  The Program Counter contains an unsigned integer as the address of the next instruction in memory. A Program Counter is incremented by an integer, provided that all the instructions have the same length. It is possible to design the IAR as a counter as long as the variable instruction length is 2n where n is 1, 2, or 4. For example, after obtaining a 4B instruction into an IR, we can add 1 to the 3rd bit on the right of the counter.

  It should be stressed that because all the instructions on a typical RISC (reduced instruction set computer) machine are four bytes long, its IAR is a counter as shown in Figure 3.3 . As each instruction is four bytes, its address is an unsigned integer with two trailing zeroes (IA1 and IA0) implied. The Program Counter contains a 30-bit block number followed by 2 zeroes and each block has four bytes. To obtain a 32-bit byte address, we append two zeroes to the 30-bit block address so that the total number of bits is 32. In hardware design, the two trailing zeroes can be hardwired so to save two flip-flops. Thus, the 30-bit block address in the Program Counter really means a 32-bit byte address with the two trailing zeroes implied. After an instruction is obtained in the IR, the 30-bit Program Counter is incremented by one. The byte address is incremented by four (22 ).

  Figure 3.3 Instruction address register as a 30-bit counter.

  On a Program Counter, the instruction length may vary from 1 to 7 bytes, but the IAR can be designed as a counter provided that the IU increments its value right after interpreting a portion of an instruction. After the entire instruction is executed, the IAR contains the address of the next instruction in memory. For this reason, we will use Program Counter and IAR interchangeably in this book.

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